Intelligent probe alarm trigger sequence diagram

4. Set the ontime pin timing of rel output

When the probe detects the human body movement signal, it will output a high level on the rel pin. The duration of this level is determined by the level applied to the ontime pin. If there are multiple trigger signals generated in the rel high level device, as long as a new trigger signal is detected, the rel time will be reset, and then the timing will be repeated.

4.1 if the analog rel timing mode is adopted, the ontime pin connects a resistance R to the power supply, and the resistance can be adjusted within the range of 100k O ~ 510k O. When the analog timing is adopted, the ontime pin will have corresponding oscillation frequency. The analog timing time td =, f is the oscillation frequency. If a longer timing time is needed, the ontime pin can be connected to the resistance R to the power supply, while the ontime pin is connected to the capacitance C to the ground. Different capacitors can be selected according to the demand, but the capacitance value cannot be greater than 10nf, the resistance value is not greater than 510k O, not less than 100k O.

The working current is related to the selected resistance R. the larger the resistance is, the smaller the working current is. If high power consumption is required, it is recommended to select a large resistance (300k-510k) or digital rel timing mode. In order to obtain the accurate timing time, we can choose the appropriate capacitance resistance value, calculate the timing time according to the oscillation frequency, and then adjust the capacitance resistance parameters.

Fig. 1 no capacitance connected to ontmie pin

Fig. 2 ontmie pin connected to 10PF capacitance to ground

Fig. 3 ontmie pin connected to 560pf capacitor to ground

Fig. 4 connection between ontmie pin and 1NF capacitor to ground

4.2 if digital rel timing mode is adopted, a fixed potential with the maximum value less than VDD / 2 is connected to ontime pin to realize timing. In practice, rel timing regulation can be realized in the form of resistance partial voltage, which is composed of upper partial voltage resistance RH and lower partial voltage resistance Rl (1% precision resistance is recommended for RH and RL). One recommended solution is to fix the upper partial resistance RH to 1m O, and the lower partial resistance RL is given in the table below. Refer to the table below for output timing time (TD) and voltage settings. Note: when digital rel timing mode is adopted, the voltage of the ontime pin must not be higher than VDD / 2. If the voltage value required for the timing time is at the critical point of the upper and lower gear division, timing time jump may occur; and the timing time can only be one of the 16 times in the table below. If the time in the table below is not appropriate, it is recommended to select analog rel timing mode.

Time gear setting time (s)

(typical value) time pin voltage range center value recommended value of partial resistance (accuracy ± 1%)

Pull up resistance RH pull down resistance RL

1 2 0 ~ 1 / 32vdd 1 / 64vdd not pasted / 1m 0r

2 5 1/32VDD~2/32VDD 3/64VDD 1M 51K

3 10 2/32VDD~3/32VDD 5/64VDD 1M 82K

4 15 3/32VDD~4/32VDD 7/64VDD 1M 124K

5 20 4/32VDD~5/32VDD 9/64VDD 1M 165K

6 30 5/32VDD~6/32VDD 11/64VDD 1M 210K

7 45 6/32VDD~7/32VDD 13/64VDD 1M 255K

8 60 7/32VDD~8/32VDD 15/64VDD 1M 309K

9 90 8/32VDD~9/32VDD 17/64VDD 1M 360K

10 120 9/32VDD~10/32VDD 19/64VDD 1M 422K

11 180 10/32VDD~11/32VDD 21/64VDD 1M 487K

12 300 11/32VDD~12/32VDD 23/64VDD 1M 560K

13 600 12/32VDD~13/32VDD 25/64VDD 1M 634K

14 900 13/32VDD~14/32VDD 27/64VDD